Research / Current / Software for Emerging Hardware

I am currently interested in developing software tools for working with emerging hardware technologies. Included in this class of hardware are architectures that use resistive memories (ReRAM, FeRAM, PCRAM), and architectures that use emerging fabrication processes (SCEs, CNFET-based architectures, Monolithic architectures, etc.). Potential software artifacts may include hardware algorithms (e.g., read/write, calibration algorithms), characterization and self-test procedures, hardware/technology-aware compilation procedures, analysis-amenable hardware models, and new programming models. An overarching goal of this research is to fully explore the capabilities of hardware platforms that make use of emerging hardware technologies.

This may be accomplished by transforming programs to reduce the effect of hardware non-idealities, developing computational models that can be effectively implemented given the constraints of an emerging hardware technology, and developing compilation techniques that effectively map programs to the target hardware.

Systematic Characterization and Modeling of Resistance-based Non-Volatile Memories

Hardware designers use device characterization data and empirically fitted behavioral models to inform the development of read/write algorithms and level allocations for multi-level non-volatile memories. To make these models tractable, designers will sometimes approximate non-idealities (e.g., approximate with normal distribution) when constructing these behavioral models. However, if these modeling approximations discard relevant empirical behaviors, then hardware algorithms built on these models may yield suboptimal results.

We are currently developing a device characterization and empirical modeling tool that identifies which modeling approximations can be safely made for a given memory technology. We have exercised an initial prototype of this tool on a fabricated ReRAM chip and extracted an analog behavioral model. Preliminary results show that we can elicit more accurate MLC ReRAM level allocations with our behavioral model.